Ovonic unified or phase-change memories are an emerging type of electrically-alterable non-volatile semiconductor memory. These memories exploit the properties of materials (phase-change materials) that can be reversibly switched between an amorphous phase and a crystalline phase. A phase-change material exhibits different electrical characteristics, particularly a different resistivity, peculiar of each one of the two phases; thus, each material phase can be conventionally associated with a corresponding one of the two logic values, “1” and “0”. An example of a phase-change semiconductor memory is described in U.S. Pat. No. 5,166,758.
Typically, the memory includes a matrix of phase-change memory cells, arranged in rows and columns with associated word lines and bit lines, respectively. Each memory cell consists of a storage element connected in series to an access element; as the access element, the base-emitter junction of a bipolar junction transistor, particularly a PNP BJT, associated with the storage element can be used.
In a stand-by condition, or before any read or write access to the memory, the word lines are kept at a relatively high voltage (word line deselection voltage), so that all the access elements are reverse biased.
During a write or read operation, the voltage of a selected word line is lowered, and one or more selected bit lines are brought to a voltage corresponding to the operation to be performed, while the remaining, non-selected bit lines are left floating. In this condition, the access elements associated with the memory cells of the selected word line and of the selected bit lines are forward biased, and the access to the corresponding storage elements is enabled.
However, leakage currents inevitably flow through the access elements even when they are reverse biased; the leakage currents, delivered to the access elements by the word line drivers, cause the charging of stray capacitances intrinsically associated with the bit lines, and the voltage of the bit lines raises, therefore, towards the word line deselection voltage.
If, as a consequence of the leakage currents, the voltage of a generic bit line reaches and, possibly, exceeds the turn-on voltage of the access elements (the threshold voltage of the base-emitter junction diodes, typically 0.6 V), an undesired access to the storage element that belongs to such a bit line and to a selected word line takes place, even if the bit line is actually kept unselected.
In this condition, the current flowing through the spuriously selected storage element may cause the voltage of the selected word line to rise, disturbing the operation of the memory device. Even worse, when the current flowing through the spuriously selected storage element reaches a value sufficient to cause a switch of phase in the phase-change material, the phase switch can cause an undesired change of the logic value stored in that memory cell. Even when the phase switch is only temporary and not permanent, a wrong value can be read if the memory cell is selected before a corresponding recovery time.
These problems are exacerbated as the temperature increases, since the leakage currents typically depend on the temperature according to an exponential law. In addition, the total leakage current injected into each storage element in the selected word line is directly proportional to the number of access elements in the corresponding deselected bit line.
For these reasons, before any operation involving the selection of a word line, the bit line voltage has to be brought to a properly low value, typically to ground, and thus the bit line stray capacitances need to be discharged. To this purpose, controlled switching elements, typically pass transistors, are associated with the bit lines, which are activated during a bit line discharge phase preceding any operation that involves the selection of a word line, so as to electrically connect the bit lines to a reference voltage line, for example, the ground line, and to discharge the associated stray capacitances.
A problem arises when, due to a manufacturing defect, a short-circuit (or, generally, a low-resistance path) exists between a generic bit line and a generic word line of the matrix. Especially in very dense memory matrices, this type of defect may be relatively highly probable. Known redundancy techniques allow repairing such a defect, by functionally replacing the defective bit line and word line with redundant bit line and word line; any attempt of selecting the defective bit line and word line would automatically result in a selection of the redundant bit line and word line.
Regreffully, according to the known approach, during the bit line discharge phase, before the desired word line is selected (thus, when all the word lines are still kept at the word line deselection voltage), the short-circuit between the defective word line and bit line causes a short-circuit between the word line driver supply voltage line (the line supplying the word line deselection voltage to the word line driver) and the reference voltage line; this short-circuit causes the flow of a significant crowbar current, for a time corresponding to the activation time of the bit line discharge pass transistors (typically, some tens of nanoseconds). This may easily cause the memory to exhibit an unacceptably high power consumption. Additionally, when the word line deselection voltage is generated on-chip by means of charge-pump voltage generators, the excessive current absorption due to the short circuit may easily cause the charge-pump output voltage to fall below a safety level, with the consequence that the correct operation of the whole memory might be prejudiced (for example, a too low word line deselection voltage may prevent the proper deactivation of the memory cell access elements, with the possible consequence that the data stored in the memory cells of the selected bit line are corrupted).